Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One prior art non-volatile memory cell 10 is shown in FIG. 1. The split gate flash memory cell 10 comprises a semiconductor substrate 4 of a first conductivity type, such as P type. The substrate 1 has a surface on which there is formed a first region 2 (also known as the source line SL) of a second conductivity type, such as N type. A second region 3 (also known as the drain line) also of a second conductivity type, such as N type, is formed on the surface of the substrate 1. Between the first region 2 and the second region 3 is a channel region 4. A bit line (BL) 9 is connected to the second region 3. A word line (WL) 8 (also referred to as the select gate) is positioned above a first portion of the channel region 4 and is insulated therefrom. The word line 8 has little or no overlap with the second region 3. A floating gate (FG) 5 is over another portion of the channel region 4. The floating gate 5 is insulated therefrom, and is adjacent to the word line 8. The floating gate 5 is also adjacent to the first region 2. A coupling gate (CG) 7 (also known as control gate) is over the floating gate 5 and is insulated therefrom. An erase gate (EG) 6 is over the first region 2 and is adjacent to the floating gate 5 and the coupling gate 7 and is insulated therefrom. The erase gate 6 is also insulated from the first region 2.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate EG 6 with other terminals equal to zero volt. Electrons tunnel from the floating gate FG 5 into the erase gate EG 6 causing the floating gate FG 5 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate CG 7, a high voltage on the source line SL 2, a medium voltage on the erase gate EG 6, and a programming current on the bit line BL 9. A portion of electrons flowing across the gap between the word line WL 8 and the floating gate FG 5 acquire enough energy to inject into the floating gate FG 5 causing the floating gate FG 5 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as ‘0’ state.
The cell 10 can be inhibited in programming (if, for instance, another cell in its row is to be programmed but cell 10 is to not be programmed) by applying an inhibit voltage on the bit line BL 9. The cell 10 is more particularly described in U.S. Pat. No. 7,868,375, whose disclosure is incorporated herein by reference in its entirety.
Also known in other areas of art are three-dimensional integrated circuit structures. One approach is to stack two or more separately packaged integrated circuit chips and to combine their leads in a manner that allows coordinated management of the chips. Another approach is to stack two or more dies within a single package.
However, to date, the prior art has not included three-dimensional structures involving flash memory.